The present invention is related to a transmission system comprising a first node for transmitting packets in a synchronous frame to a second node. The invention is also related to a transmitter, a receiver, a method and a signal.
A transmission system according to the preamble is known from ITU-T Standard G.804.
Such transmission systems are applied where packet switched data such as ATM data has to be transmitted over a synchronous data link said such as a PDH (Plesiochronous Digital Hierarchy) or SDH (Synchronous Digital Hierarchy) link. This can be useful for transmitting video information in ATM format over an existing transmission path using PDH or SDH. For such transmission the packets are embedded in the synchronous signal in a prescribed manner. One way of embedding ATM packets is prescribed in the above mentioned G.804 standard. In the above mentioned standard it is not prescribed how to transfer accurate timing information in said ATM packets.
The object of the present invention is to provide a transmission system according to the preamble in which it is possible to transfer accurate timing information in said packets.
To achieve this object the present invention is characterized in that the second node comprises timing extraction means for extracting a timing signal when a predetermined symbol in a packet is transmitted in a predetermined position in the frame.
The present invention is based on the recognition that it is possible to extract accurate timing information from the signal if this timing signal is extracted when a predetermined symbol in a packet appears at a predetermined position in the frame. In the example of carrying ATM packets in G.704 frames, 53 bytes ATM packets are carried in a plurality of frames, each of them carrying 30 bytes. In this case the first byte of an ATM cell coincides with the first byte of a G.704 frame each 53 frames. With a frame period of 125 xcexcs, said first byte of an ATM packet will coincide with the first byte of a frame each 53xc2x7125 xcexcs 6.625 ms.
Consequently an accurately defined timing signal can be obtained from the ATM signal by generating a timing signal at the instant on which the first byte of an ATM frame corresponds to the first byte of a G.704 frame.
An embodiment of the invention is characterized in that the first node comprises timing information transmission means for transmitting a clock reference value to the second node, and in that the second node comprises synchronization means for synchronizing at arrival of the timing signal a local clock with the clock reference value.
In this embodiment of the invention it is possible to synchronize a local clock in the second node with a clock in the first node. Both clocks can have a frequency which is unrelated to the clock frequencies involved with the signals transmitted over the transmission path.
A further embodiment of the present invention is characterized in that the timing reference value corresponds to an expected clock value at arrival of the next timing signal at the second node.
In this embodiment, the clock in the second node can easily be set to the timing reference value received earlier. This in a very simple and effective way to synchronize the clock in the second node to the clock in the first node.
A still further embodiment of the present invention is characterized in that the second node comprises clock information transmission means for transmitting a clock reference value derived from its local clock to the first node, in that the first node comprises adaptation means for adapting the clock reference value in dependence on the clock reference received from the second node.
This embodiment allows the automatic compensation of the transmission delay between the two nodes. If a transmission delay D is present between the first and second node, the clock in the second node will be a time D behind the clock in the second node, because the timing signal arrives a time D later at the second node than the arrival time assumed by the first node.
By transmitting to the first node, a clock reference signal derived from the clock in the second node, a clock reference signal is received by the first node being 2D later than the clock reference in the first node. By comparing the present clock value in the first node with the clock reference signal transmitted by the second node the value of D can be determined by the first node. Consequently the first node can adapt the clock reference value transmitted to the second node to compensate for the measured delay.